This is a master level course on Computer Architecture. The objective is to study the architectural
concepts and to understand some of the issues of current computer architecture and design
(microarchitecture). The primary attention of the course will be on performance enhancement. The power and
energy efficient architecture will also be discussed. The course has companion CS5292 as a laboratory course
where the programming, simulator (design and use), and analysis related exercises will be carried out.
Here is the course content: cs5202 content.
Here is a link to laboratory course: cs5292
Following would be the tentative lecture plan.
| Lecture 0 (Jan 14): | Organisational meeting; Presentation, Handnotes
Additional material:
- Moore law: past, present and future, IEEE spectrum, June 1997.
IEEE Explorer
- Gordon Moore, Intel-Memories and the Mircoprocessor, MIT Press 1996.
jstor link
|
| Lecture 1 (Jan 16): | Performance modeling and measurement; Presentation, Handnotes
Additional material:
|
| Lecture 2 (Jan 21): | Benchmark program and reporting/summarising performance;
Presentation, Handnotes
Additional material:
- Chapter 1, Computer Architecture: A Quantitative approach, 5th/6th Edition
- J.E. Smith, Characterizing Computer Performance with a Single Number, CACM Volume 31, Issue 10 (October 1988), pp.1202-1206
- Lecture notes of Prof Milo
|
| Lecture 3 (Jan 23): |
Measuring and modeling the power and energy consumption;
Additional material:
|
| Lecture 4 (Feb 4): | Memory system concept and design; Presentation
Reading Materials:
- Chapter 5, Implementation Issues; Memory Systems: Cache, DRAM, Disk;
Bruce Jacob .
- This lecture has been merged with Memory System design
|
| Lecture 5 (Feb 11): | Instruction set principles Presentation
Reading Materials:
- Appendix A: Instruction Set Principles; 5th/6th Edition of Computer Architecture
Quantitative Approach.
|
| | Practice problem sets:
From 2019 course:
|
| Lecture 6 (Feb 13): | Comparison of ISAs (RISC-V, X86, ARM) Presentation
Reading Materials:
- RISC-V: Appendix A and Appendix K , Computer Architecture Quantitative Approach, 6th Edition.
- MIPS: Appendix A and Appendix K , Computer Architecture Quantitative Approach, 5th Edition.
- (ARM64: Read from the ARM ISA manual (This will not be part of theory syllabus, this will be explored in Laboratory.))
- X86_64: Appendix K , Computer Architecture Quantitative Approach, 5th/6th Edition.
|
| Lecture 7 (Feb 18): | Cache Memory Architecture: Presentation Handwritten notes
Reading Materials:
- Appendix B: Review of Memory Hierarchy, Hennessy and Patterson, Computer Architecture Quantitative Approach, 5th Edition
- Chapter 5: Exploiting Memory Hierarchy, Patterson and Hennessy, Computer Organisation and Design, 5th Edition or ARM Edition
|
| Lecture 8 (Feb 20) : | Cache Memory Operations: Four Questions Presentation
Reading Materials:
- Appendix B: Review of Memory Hierarchy, Computer Architecture Quantitative Approach, 5th Edition.
- Case study: AMD Opteron Data Cache
|
| Lecture 9 (Feb 27): | Cache Memory Performance and Optimization Handwritten Notes | Problem set 9.1
Reading Materials:
- Appendix B: Review of Memory Hierarchy; Computer Architecture Quantitative Approach, 5th Edition.
- Chapter 2: Memory Hierarchy Design; Computer Architecture Quantitative Approach, 5th Edition: Presentation
- Aspect of Cache Memory and Instruction Buffer Performance, Mark D Hill, Technical Report, UC Berkeley Link
|
| Lecture 10 (March 12): | Ten Advanced Cache Optimization Techniques Presentation
Reading Materials:
- Chapter 2: Memory Hierarchy Design; Computer Architecture Quantitative Approach, 5th Edition
- Lecture notes of Prof David Brooks could also be referred.
|
| Lecture 11 (Mar 17): | Main Memory: Design and Architecture, Presentation
Reading Material:
- Bruce Jacob, Spencer Ng, and David Wang; Memory Systems: Cache, DRAM, Disk;
2008, Elesevier. (Refer: Chapter 10 and Chapter 8)
- Onur Mutlu, Scalable Memory System Lectures, Lecture 1, Lecture 2 and Lecture 3;
Link
- Text Book (H&P): Memory Technology and Optimization, Chapter 2.
|
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| Lecture 12 (Mar 17): | Virtual Memory System; Presentation
Reading Material:
- Patterson and Henessay;
Computer Organization and Design: Hardware/Software Interface, 5 th Edition
(Refere Chapter 5, Section 5.7)
- Henessy and Patterson; Computer Architecture: Quantitative Approach,
(Refer Chapter 2)
|
| Lecture 12 (Mar 17): | Home Task: Virtual memory case study: ARM and Intel
Reading materials:
- ARM Cortex A8 Vs Intel Core i7: Memory Hierarchy from Text book.
|
| Lecture 13 (Mar 19): | Instruction level parallelism: Presentation
Reading material:
- Preliminary on Pipeline architecture: Presentation
- Appendix C: Henessy and Patterson, Computer Architecture Quantitative Approach
- Chapter 4: Patterson and Henessy, Computer Organisation and Design
- N Jouppi and D Wall, Available Instruction Level Parallelism for
Superscalar and Superpipeline Machines, WRL Research Report 89/7
|
| Lecture 14 (Mar 24): | Superscalar architecture: Introduction Presentation
Reading materials:
- Chapter 4: Shen and Lipasti, Modern Processor Design
|
| Term projects (Mar 30): | List of projects List
Reading materials:
- Shen and Lipasti, Modern processor design
- Henessy and Patterson, Computer Architecture: Quantitative Approach, 5th or 6th Edition
- Listed literaure
|
| Lecture 15 (Mar 31): | Issues in Superscalar architecture Presentation
Reading materials:
- Chapter 5: Shen and Lipasti, Modern processor design:
- Chapter 3: Henessy and Patterson, Computer Architecture: Quantitative Approach, 5th or 6th Edition
|
| Lecture 16 (Apr 2): | Branch speculation and predictors Presentation
Reading materials:
- Advance branch prediction technique, Chapter 5, Shen and Lipasti
- Reducing branch cost with advanced branch prediction, Chapter 3, Computer Architecture: Quantitative Approach
- A PPM-like, tag-based branch predictor, Pierre Michaud, Journal of Instruction Level Parallelism, Vol 7, 2005
|
| Lecture 17 (Apr 7): | Scheduling and Memory Data flow Presentation
Reading materials:
- Superscalar Techniques, Chapter 5, Shen and Lipasti
- Chapter 3, Henessy and Patterson, Computer Architecture
|
| Syllabus for End-term test: | Test includes only Lecture 7 to Lecture 17: Syllabus
Reading materials:
- All the reading materials are listed in the document itself.
|
| Lecture 18 (Apr 9): | Thread level parallelism Introduction Presentation
Reading Materials:
- Multithreading Architecture, Synthesis Lecture on Computer Architecture
- Chapter 3, Henessy and Patterson, Computer Architecture
|
| Lecture 19 (Apr 14): | SMT-Simultaneous Multithreading Presentation
Reading Materials:
- Multithreading Architecture, Synthesis Lecture on Computer Architecture
- Chapter 3, Henessy and Patterson, Computer Architecture
|
| Lecture 20 (Apr 16): | Research in Computer Architecture, Presentation will be uploaded next |
| End of class | The course ends here, schedule for final test is based on the
Covid situation! |
| Lecture 21 (TBS): | Multiprocessor: Shared memory architecture | |
| Lecture 22 (TBS): | Synchronization and Memory consistency | |
| Lecture 23 (TBS): | Vector architecture | |
| Lecture 24 (TBS): | SIMD and Graphics processing unit | |
| Lecture 25: | Discussion 1: Project and problem set | |
| Lecture 26: | Discussion 2: Project and problem set | |