Jaynarayan Thakurdas Tudu

friends call me as Jaynarayan or just Jay (much shorter version 'J')!
Workplace: 2nd Floor, Annex Building, Temporary Campus, IIT Tirupati.


Covid-19 Research   |   JRF opening

Research

Our research focuses on Reliable and Energy-aware Computing Hardware. The concept of reliability requires a hardware system to be free from any defect that may leads to erroneous system behavior. And, energy-aware principle requires the hardware system to be aware of efficient use of energy as and when needed without compromising on accuracy and performance. Our research focuses on Design, Test and Verification of intelligent computing hardware. For the next generation intelligent hardware the energy efficiency and reliability would be crucial and what we need is to explore a newer thought and approach. The intelligent hardware system would be consisting of redundancy and massive parallelism inherently and this would turn the thought process differently when we address the issues of reliability, energy efficiency and accuracy. The intelligent hardware system would span across the different application domains starting from edge devices to high performance processor. Our interest lies in investigating the AI accelerators in edge nodes in IoT system, in hand-held device and in personal computing machine.

Future perspective: the never-ending human endeavor has thought to make the machines as intelligent as the best human being and as efficient as the best machine. While attempting to find such machine the human so far has reached from where we could imagine the next generation computing machine to be fully autonomous. What does it mean? It means that a machine which would be capable of making decision, which is cognizance of surroundings, and everything that is amazing about human being, is the dream of next gen society. Therefore, our research take interest in investigating the dependable aspects of such machine. While investigating in this domain we take a look at the dependable processor architecture and design, and autonomous CAD tools for the next gen computing hardware.

Research Area:

Dependable Computing

AI Hardware

Power-aware Test of VLSI SoC
Joint-scan DfT (Design for Test) Architecture
Extreme Low-energy Testing of IoT node
Accuracy-aware testing of AI Accelerator
Approximate and Application Specific Test
Hardware-software Co-verification
Post-silicon Debug and Diagnosis
Fault-tolerant and Reliable Design
Dependability in Reconfigurable Computing (FPGA)
Reconfigurable AI Accelerator
Approximate and LowEnergy Deep Neural Network
AI Chip for TinyML
Hardware Architecture for GraphProcessing
AI Hardware-Software Co-design
CAD tools for AI Hardware
Brain-like Processor Design
(Slow but Massive Accelerator)

Ongoing Research:

Joint-scan DfT Architecture:
The joint-scan architecture a highly power-efficient DfT architecture which can be configured as a internal scan architecture to test SoCs. The architecture needs to be evaluated for TDF test for both the LoS and LoC mechanism. Further a compiler need to be designed to insert this scan architecture into the netlist of a design. The research also aims to reduce the routing congestion and area due to the architecture.

Extreme Low-power Test Methodology:
There are many SoC designs (small and big) whose power, energy and area constraints are highly stringent. Testing such designs, particularly while they are operational in field, poses several challenges with respect to power and energy dissipation. Some of the IoT sensor nodes are of such kind, which requires to be tested at extreme low power with nominal energy consumption. Therefore, the traditional low power test methodology can not be applied as such. Our research investigate such problems for different applications and operating environment (such as PVT and performance).

Test Methodology for ML Accelerators:
The objective is find out the test methodology for machine learning based accelerators which are specific to the applications. The traditional test methodology would be highly inefficient for the design of this kind whose accuracy depends highly on the structure of hardware circuit. The idea is to develop a new metric to say that whether the given design is faulty, fault-free or probabilistically faulty.

Test Cost Minimization:
The research is to solve the problem of defect prediction. And, further use the defect prediction to minimize the test cost. Currently we are exploring the possibility of adaptive test set ordering as a technique to minimize the test cost. The research make use of learning and statistical techniques for prediction and adaptive ordering.

Dark Silicon and Fine-grained Power Gating:
This work explore the application specific power gating in the multi-core setting. The final objective is to solve the so called Dark Silicon problem to ensure the safe functioning of all the cores in a chip. The fine-grained power gating has a numerous roadblocks such as power-up delay, area overhead, modularization of the design, and finally the design of gating cell. These problem need to be solved to get the benefit of fine-grained power gating.

UG and Master Project

These projects typically can be completed in a semester or in a couple of semesters time. A single person effort is sufficient for these projects, however, some of the work might require a group efforts. Description and how to go about on the projects could be found here.

Teaching

Publication

Some of our publications could be found in [gscholar] and in [dblp].
Exhaustive list which includes the workshop publications: my list

Tool

The source code and other detail of the tools will be updated in github repo and also here in this site soon. The related publications could be found in Publication.

Research Group

UG Students:
Madhava and Prashant; Project: Energy Efficient Accelerator for Machine Learning [2019-2020](Currently with Nviera)
Sandeep; Project: Hardware Synthesis Compiler for Joint-scan DfT Architecture [2019-2020] (Curently with Nviera)

Akash Gupta; Project: Application Specific Power Management in Multi-core Architecture [2018 - 2019] (Working towards a Startup)
Teja Ramana; Project: Application Specific Power Management in Multi-core Architecture [2018 - 2019] (Currently with Waycool)
Ashwin Prakash; Project: Power-aware Dynamic Pipeline Architecture [2018-2019] (MS-PhD Candidate at Courant Institute)
Master Students:
Pankaj Kumar Dwivedi; Project: Application Specific Thread Scheduling in GPU [2020 - 2021] (Currently with Redpine Signals)
Brijesh Kumar Dubey; Project: Energy-efficient Algorithm to Test Defects in Edge Nodes in IoT [2020 - 2021] (Currently working for Software Industry)
Subir Kumar Parida; Project: Formal Verification of Memory Controller [2019 - 2020] (Jointly with Prof. Ravi Iyer)
Richa Chaudhury; Project: Power Profiling of Machine Learning and Graph Applications [2019 - 2020]

Students interested to work with us could write email or meet us in office.


Collaboration

Currently with CADS Lab, IIT Bombay.

We are in the process of collaboration with few other professors, once the research problems are set we will update the details. In past we are lucky enough to collaborate with some of the leading professors:

Forums

The reliable computing in the CMOS VLSI has a history of around 60 years. There has been many forums which were created as demanded by time. The average age of the conferences and journals is of 30 years old. Some of the active conference and journals are listed here. The list include conferences and journals from VLSI Test, Verification, CAD for VLSI, Fault Tolerant Architecture and Computer Architecture.


News

Research:
[June 2020] All the UG/PG projects are presented/defended by the students.
[Jan 2020] No exciting news these months!
[Nov 2019] Keynote address on "Hardware Security: State of the Art" presented by myself in FDP at KSRM, Kadapa.
[Oct 2019] A proposal on "Intelligent Test and Reliability Architecture" got approved by DST-SERB.
[2 Oct 2019] Dr. Satdev presented our work at DFT-2019, Netherland.
[20 July 2019] A paper titled: "Preventing Scan Attack through Test Response Encryption" got accepted in DFTS - 2019
[4 July 2019] Prof. Virendra Singh presented our work at IOLTS-2019
[20 May 2019] Akash, Teja and Ashwin presented their BTP (BTech Project)
Miscellaneous:
Due to pandemic of Covid the lectures are being conducted via online, video lectures, slideshare, classroom.
Myself presented a workshop on "What is Consciousness" at IISc, Bangalore organised by Student of IISc and Bhaktivedanta Institute Bangalore.
An interview of Prof Raj Reddy - a visionary academician who brought many computer science ideas and technology to society. Interview
First CNFET (carbon nano tube FET) based microprocessor:Nature.com
Presented a talk to the freshers of IIT Tirupati on Counting to Computing [presentation]
Articulate your research (PhD/PDF): dst india
Smart Mobility problem and solution: MoveHack.
Research and Innovation: Innovate:
Upcoming Research Meetings: Link

About Me

My education and academic detail can be found here in my vitae .

When I don't do research I spend time in learning science and super-science, you can find more here.


You could email us at: jtt[at]iittp[dot]ac[dot]in or
call us on: nine eight eight six three zero five four one zero / nine one zero zero eight six one seven seven one.

Thank You!