Computer System Design Laboratory (CS4110)

Dept of Computer Sci and Engg
Indian Institute of Technology Tirupati, India

Course plan could be found here.

The companion theory course: cs4100

[19th Aug, 2019] Design Experiment 1: Digital Building Blocks

[27th Aug, 2019] Design Experiment 2: ALU and Component Design

[3rd Sep, 2019] Design Experiment 3: Sequential Elements

[17th Sep, 2019] Design Experiment 3b: Memory System Design

[15th Oct, 2019] Programming Experiment 4: Assembly/Machine Language Programming

[22nd Oct, 2019] Processor Design Experiment 5: 16 bit Processor Design

[5th Nov, 2019] System Design Experiment 5b: Computer System Design with Data and Ins Memory

[5th Nov, 2019] Design Experiment 6: Assembler Design

[13th Nov, 2019] Design Experiment 7: VM Translator Design

[19th Nov, 2019] Design Experiment 8: Design Integration: A Complete System Design

Useful Resources

Nand2Teris course repository: Home link

ModelSim (for Design and Simulation using Verilog and VHDL): Mentor Page