Computer System Aarchitecture (CS5292)

Dept of Computer Sci and Engg
Indian Institute of Technology Tirupati, India


This is a laboratory course of CS5202.
Here is the laboratory course content: cs5292 content.
Here is a course plan: cs5292

Following would be the tentative Experiment plan.
Experiment 0: Study of code size in RISC (ARM and RISC-V) and CISC (x86 64) instruction set.
Experiment 1: Performance Evaluation Metrics: Arithmetic Mean, Geometric Mean, and Standard Deviation.
Experiment 2: Memory architecture: Impact of size, block size and page fault.
Experiment 3: Cache memory: Study of cache size, levels, associativity.
Experiment 4: Pipeline Processor Architecture: to experiment on the optimal number of pipeline stages.
Experiment 5: Branch Predictor: to study the impact of branch predictor on performance.
Experiment 6: Installation of Snipper, Pin, GEM5, SimpleScalar, MacPat and other tools.
Experiment 8: Execution of bench mark programs on Sniper with different configuration for single core architec- ture.
Experiment 9: Snipper simulation for multi-core architecture using configuration file.
Experiment 10: Code modification and architecture implementation in Snipper.
Experiment 11: Experimenting with the power dissipation (with MacPat and Snipper).
Experiment 12: GPU characterization using GPGPU-sim simulator.

Useful Resources

This will be updated
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