The VLSI technology has evolved to a situation where it has become necessary to understand the failure mechanism of a given circuit and a system at large. Due to two main reasons, the downscaling of technology and complexity of the design, the failure of a given circuit have become most common and hard to understand. The study show that the failure of the circuit would further increase as the technology goes towards nm region (already 14 nm has been manufactured). Further, the complexity of the design tends to bring more design bug than before. Therefore to have an error free design and a defect free chip it has become essential practice to carry out design verification and manufacturing test as part of the VLSI design cycle. These two activities have become mandatory task for any modern design.

The course would focus on teaching and training of the students to learn the VLSI circuit failure mechanism, algorithm, modeling, and simulation of the defects and design bugs. The course has two parts: testing and verification. The testing would cover the issues that arises due to manufacturing of the chip and the verification would cover the issues that arises due to design. The course would train the student to design algorithm and tools while exposing them to the existing EDA tool set. The following are some of the topic that would be taught in this course. Fundamental of testing: vlsi design process, defect and fault model, logic and fault simulation, test generation algorithm, testability measures, test economy, and test equipment; Design for testability: scan design, built-in-self-test (BIST), boundary scan architecture, SoC test; Delay test: fault model, pattern generation, scan based delay test, and small delay defects; Memory testing: functional fault model, memory test algorithm, memory BIST and meory diagnosis; Test optimisation: test compression and power aware test; Verification: dynamic verification, formal equivalence checking, binary decision diagram, finite automata, formal properties checking, temporal logic, timing verification, and hardware emulation.

The students of this course would be capable of designing algorithms for test and verification and be able to use the EDA tools to meet the design specification. The students also would gain insight on how to diagnose a defect and design bug. The student further would be prepared to carry out research in this area.