Publications

Proceedings and Journals

2019

• Satyadev Ahlawat, Jaynarayan Tudu, Masahiro Fujita, Virendra Sing, "Preventing Scan Attack Through Test Response Encryption", Proc of 32nd IEEE Intl Symposium on Defect and Fault Tolerant in VLSI and Nanotechnology System (DFT-2019), Netherland [To be published]
• Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan Tudu, Masahiro Fujita, Virendra Singh, "Securing Scan through Plain-text Restriction", Proc of 25th IEEE Intl Symposium on Online Testing and Robust System Design (IOLTS-19), Rhodes Island, Greece.[To be published]

2018

• Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, Virendra Singh, "A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test", IEEE Transaction on Device and Materials Reliability, Vol. 18 (2), 2018.
• Darshit Vaghani, Satyadev Ahlawat, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, "On Securing Scan Design Through Test Vector Encryption", IEEE International Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy, May 27-30, 2018.

2017

• Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, and Ashok Suhag, "A Cost Effective Technique for Diagnosis of SCan Chain Faults", 21st International Symposium on VLSI Design and Test (VDAT 2017)}, Roorkee, India, June 29 - July 2, 2017. Communication in Computer and Information Science, Vol 711, Springer, Singapore, pp. 191-204.DOI.
• Binod Kumar, Ankit Jindal, Jaynarayan Tudu, Brajesh Pandey, Virendra Singh, "Revising Random Access Scan for Effective Enhancement of Post-silicon Observability", 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)}, Thessaloniki, Greece, July 3-5, 2017, pp. 132-137.
• Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, Virendra Singh, "On Securing Scan Design from Scan-Based Side-Channel Attacks", 26th IEEE Asian Test Symposium (ATS)}, 2017, Taipei, Taiwan, November 27-30, 2017. DOI: \url{TBA}.

2016

• Binod Kumar, Ankit Jindal, Boda Nehru, Brajesh Pandey, Jaynarayan Tudu and Virendra Singh, "A Technique for Low Power, Stuck-at Fault Diagnosable and Reconfigurable Scan Architecture", IEEE East-West Design and Test Symposium (EWDTS) 2016, Yerevan, Armenia, October 14-17, 2016. DOI.
• Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, "A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test", IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2016, Catalunya, Spain, 4-6 July, 2016, pp. 233-238. DOI.
• Jaynarayan Tudu, "JSCAN: A Joint-scan DFT Architecture to Minimize Test Time, Data Volume, and Test Power", 20th IEEE International Symposium on VLSI Design and Test (VDAT) 2016}, Guwahati, India, May 24-27, 2016. DOI.
• Jaynarayan Tudu and Satyadev Ahlawat, "Guided Shifting of Test Pattern to Minimize Test Time in Serial Scan", 20th IEEE International Symposium on VLSI Design and Test (VDAT) 2016}, Guwahati, India, May 24-27, 2016. DOI.
• Satyadev Ahlawat and Jaynarayan Tudu, "On Minimization of Test Power through Modified Scan Flip-flop", 20th IEEE International Symposium on VLSI Design and Test (VDAT) 2016}, Guwahati, India, May 24-27, 2016. DOI.
• Binod Kumar, Boda Nehru, Brajesh Pandey, and Jaynarayan Tudu, "Skip-scan: A Methodology for Test Time Reduction", 20th IEEE International Symposium on VLSI Design and Test (VDAT) 2016}, Guwahati, India, May 24-27, 2016. DOI.
• Rohini Gulve, Nihar Hage, and Jaynarayan Tudu, "On Determination of Instantaneous Peak and Cycle Peak Switching using ILP", 20th IEEE International Symposium on VLSI Design and Test (VDAT) 2016}, Guwahati, India, May 24-27, 2016. DOI.

2015

• Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosava, Virendra Singh, "A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan", 24th IEEE Asian Test Symposium (ATS) 2015}, Mumbai, India, Nov 22-25, 2015. DOI.

2013

• Jaynarayan Tudu, Deepak Malani, Virendra Singh, "Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP", 17th International Symposium on VLSI Design and Test(VDAT), 2013}, Jaipur, India. Communication in Computer and Information Science, Springer, Vol. 382, pp. 345-352. DOI.

2012

• Jaynarayan Tudu, Deepak Malani, and Virendra Singh, "ILP Based Approach for Input Vector Controlled Toggle Maximization in Combinational Circuits", 16th International Symposium on VLSI Design and Test (VDAT) 2012}, Kolkata, India, July 2012. Lecture Notes in Computer Science, vol 7373, Springer, Berlin, Heidelberg, pp. 172-179. DOI.

2010

• Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, "Scan Cell Reordering to Minimize Peak Power During Test Cycle: A Graph-theoretic Approach", 15th IEEE European Test Symposium (ETS) 2010}, Prague, Czech Rep., May 24-28, 2010. DOI.
• Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, "Graph-theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power", 20th ACM Great Lake Symposium on VLSI (GLSVLSI) 2010}, Providence, Rhode Island, USA, May 16-18, 2010. DOI.

2009

• Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Adit Singh, "Capture Power Reduction for Modular System-on-Chip Test", IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July, 2009. DOI: Not available.
• Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Vishwani D. Agrawal, "On Minimization of Peak Power during SoC Test", 14th IEEE European Test Symposium (ETS) 2009}, Seville, Spain, May 24-29, 2009. DOI.
• Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, and Virendra Singh, "Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation",\textit{IEEE East-West Design and Test Symposium (EWDTS) 2009}, Moscow, Russia, September 2009. DOI: Not Available.

Workshops

• Binod Kumar, Ankit Jindal, Jaynarayan Tudu, and Brajesh Pandey, "An Integrated solution for manufacturing testing and post silicon validation", 8th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2017, Hyderabad, Jan 2017.
• Binod Kumar, Ankit Jindal, Jaynarayan Tudu and Virendra Singh, "A Methodology For Post-Silicon Debug Utilizing Progressive Random Access Scan Architecture", 17th IEEE Workshop on RTL and High Level Testing (WRTLT) 2016}, Hiroshima, Japan, November 24-25, 2016.
• Jaynarayan Tudu and Virendra Singh, "Guided shifting of test patterns to minimize the test time in serial scan", 15th IEEE Workshop on RTL and High Level Testing (WRTLT14) 2014, Hangzhou, China, Nov 2014.
• Satdev Ahlawat, Jaynarayan Tudu, Virendra Singh, Shashidhar Bapat, and Karthik Madhugiri, "Low power scan flip-flop design to eliminate output gating overhead for critical paths", IEEE Intnl Workshop on Reliability Aware System Design and Test (RASDAT) 2012, Hyderabad, India, Jan 2012.
• Satdev Ahlawat, Ashok Suhag, Jaynarayan Tudu, and Virendra Singh, "Power aware scan flip-flop design for scan test", 13th IEEE Workshop on RTL and High Level testing (WRTLT) 2012, Niigata, Japan, Nov 2012.
• Jaynarayan Tudu, Erik Larsson, and Virendra Singh, "Test Scheduling of Modular System-on-chip Under Capture Power Constraints", 11th IEEE Workshop on RTL and High Level Test (WRTLT) 2010}, Shanghai, China, December 2010.
• Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, "Scan Cells Reordering to Minimize Peak Power during Scan Testing of SoC", IEEE WRTLT 09, Hong Kong, Nov. 2009.