The computing machines have evolved to a much faster and complex ever since the first microprocessor has been designed. The computer architecture has been driven by the nature of applications/workloads for which the computing machine is being designed. Different kind of devices have evolved in the due course of time along with the need of diverse applications. Almost nearly at the same time both, the RISC and CISC, type of architectural concepts have evolved to meet the application demand of different type. It is still a subject of research and debate that which architecture suits what kind of applications. However, the observation indicates that while the one type of architecture is good for hand-held devices the other one is good for desktop based general purpose computing. Yet there are dedicated architectures for high-performance computing. Recently, again for the same reason of application need we find two different kind of computing devices at two end of this spectrum: one is edge device while the other end is data center. In all these efforts the central issue is to achieve performance. Recently due to the popularity of hand-held devices and of course due to the CMOS device scaling the power and energy has been appearing as critical issues to achieve higher performance. These problems have become a central research agenda of many processor architects. The another trade-off that has been affecting the performance gain or loss is whether the computing machine is a general purpose or a special purpose one. The hope is that the specific purpose computing machine would be better than the general purpose one. And, it is the fact. At present we are at an interesting diversion which indicates that the general purpose processor would fetch very nominal performance improvement unlike in the last decades. Therefore, the special purpose processor become meaningful if at all the overall system performance have to be improved significantly. The domain specific architecture is an attempt in this line of thought.

The objective of this course is to teach the students the concept, architecture, and design of domain specific computing machine. The course starts with a foundational understanding and principle of the domain specific architecture which are beautifully captured by Flynn's classification and then progress to the specific topics. The specific topics includes GPGPU architecture and Vector processor which are specialized in processing the multimedia information. The course would then take up the highly demanding topics of neural network and deep neural network processor which serve as the data center accelerator: tensor flow and catapult, crest, and pixel visual core. The course would also cover the domain specific system design for data center. The teaching of the course would be delivered through lectures and laboratory experiments on programming. The course would also extensively review the research in the area of specific purpose architecture, hardware accelerator, FPGA based acceleration etc. The course would equip the students as an architect and designer of these specific accelerator. The student will be able to diagnose the issues related to performance and power dissipation of this processor. Further, the student will be also able to write and execute a code on some of these accelerators. (The course does not cover the programming extensively, however, the students will be given a chance to learn by themselves.)